This invention relates generally to a semiconductor memory circuit and more particularly to a semiconductor memory circuit suitable for improving the operation speed of the circuit, immunity to most external disturbance and reliability such as reduction of the soft error rate or higher soft error immunity.
A high speed memory circuit consisting of the combination of an MOS transistor and a bipolar transistor has been proposed in the past (e.g. Japanese Patent Laid-Open No. 129994/1980). In order to improve the operation speed of the circuit, the voltage of a data line pair is level-shifted by the emitter follower of the bipolar transistor and a diode in the memory circuit described above, is then led to a differential amplifier of the bipolar transistor and the memory data of the data line pair is amplified and then sensed. In the memory circuit described above, a plurality of constant current nodes of the differential amplifier are connected to a common constant current source, and the voltage of the data line for reading out the data is set to a higher level than the other data lines from which the data is not read out so that the current supplied from the constant current source is concentrated upon only the differential amplifier connected to the data line having a higher voltage so as to read out the data.
However, the memory circuit disclosed in the prior art reference described above does not take into consideration the influences of the memory cell on the node voltage in conjunction with the relationship between the data line voltage and the word line voltage. In this circuit, the data line voltage is led to the differential amplifier after being level-shifted, but the reference does not take into consideration the circuit arrangement wherein a plurality of emitters of level-shifting emitter followers are connected to a plurality of common constant current sources.
Furthermore, this circuit uses MOS.FET as a load device of the data lines and a data line load is formed at the time of selection and write of data line for reading out the data by ON/OFF of this MOS FET. However, the reference does not take into consideration any load devices other than MOSFET.
As described above, the conventional technique does not consider the change of the node voltage in the memory cell at the time of the read and write operations of the memory cell data, and is not free from the problems of the stable operation of the memory cell, particularly its strength against the data destruction by .alpha. rays.
Conventionally, the differential amplifier of sense amplifier is disposed on each data line. According to this circuit arrangement, however, there occurs the problem that storage of the sense amplifier inside a cell pitch of a memory cell matrix is not easy and the occupying area of the sense amplifier increases.